1. Field of the Invention
The present invention relates to a metal-oxide semiconductor field effect transistor which can be made extremely small in size and is suitable for application to LSI (large-scale integration) circuit technology, and related to methods of manufacturing such a transistor.
2. Field of the Invention
In order to produce metal-oxide semiconductor field effect transistors (abbreviated in the following to MOS FETs) which are extremely small in size and hence have a very short channel length, it is necessary to adopt countermeasures against various problems which arise as a result of the size reduction, and in particular as a result of channel length reduction. One of these problems is that during operation with a voltage applied to the gate electrode, a very high concentration of electric field is produced within the transistor at the drain pinchoff region. This results in hot-electron emission in that region, which causes problems including degradation of the current drive capability of the transistor, etc. For brevity of description, an NPN MOS transistor configuration will be assumed in the following, although the remarks are equally applicable to a PNP transistor. In the conventional form of such a transistor, the drain and source regions are formed as respective highly doped n-type regions in a p-type semiconductor substrate. Proposals have been made in the prior art for reducing the aforementioned problems which result from MOS FET miniaturization, by forming respective lightly doped n-type source and drain diffusion regions which adjoin the actual (i.e. highly doped) source and drain diffusion regions and which extend into the channel region. In this way the high electric field that is developed in the drain diffusion region of a conventional MOS FET can be spread into the lightly doped n-type diffusion region, and hence the peak value of that electric field is reduced, so that the problems described above can be alleviated. A prior art example of such a structure, called the LDD (lightly doped drain) MOS FET, is described in the IEEE Transactions on Electron Devices, Vol. ED-27, No. 8, August 1980, pages 1359 to 1367. Another prior art example of such a structure is the Inverse-T Gate structure MOS FET (referred to in the following as the inverse-TMOS FET) which is described in the IEDM Technical Digest, 1986, pages 742 to 745.
FIGS. 1 and 2 are respective cross-sectional views of the LDD transistor and the Inverse-TMOS transistor. As used herein, the term "Cross-sectional view" of a MOS FET structure refers to a cross-section which is perpendicular to the substrate major planes, and passes centrally through the drain and source diffusion regions. In each of FIGS. 1 and 2, numeral 1 denotes a p-type Si substrate, 2 denotes an electrically insulating film, and 3 denotes highly doped n-type diffusion regions which constitute the drain and source diffusion regions. (It will be assumed that each of the various MOS FET structures described herein is symmetrical, so that for :example either of the regions 3 shown in FIG. 1 could function as the drain diffusion region.) Numeral 4 denotes respective lightly doped n-type diffusion regions formed in the semiconductor substrate 1, each of which extends from one of the highly doped n-type diffusion regions 3, into the channel region as shown.
with the prior art LDD MOS FET of FIG. 1, when a high voltage is applied between the source and drain diffusion regions (i.e. each formed of one of the regions 3 together with one region 4), the depletion layer will extend through the regions 4, so that the peak value of the high electric field in the drain region will be reduced, and hence an improvement can be achieved with regard to hot-electron emission and resultant degradation of transistor performance.
With the prior art Inverse-TMOS transistor shown in FIG. 2, when a high voltage is applied between the source and drain diffusion regions, similar effects are obtained to those described above for the LDD transistor, although the Inverse-TMOS structure is described as providing an even greater improvement than is provided by the LDD structure. In addition, the shape of the gate electrode 5a of the Inverse-TMOS structure enables parasitic resistance due to depletion within the n-type lightly doped drain diffusion region 4 to be suppressed.
With such a prior art type of LDD or Inverse-TMOS FET, when a voltage is applied to the gate electrode 5a, a current can flow between the highly doped n-type drain and source diffusion regions 3, whereas when no voltage is applied to the gate electrode 5a, no current can flow between the drain and source diffusion regions. Thus such a device can operate as a MOS FET switch.
However with the prior art LDD MOS FET of FIG. 1, the following problems arise:
(1) Referring to FIG. 3, FIG. 3(a) is a partial cross-sectional view of the LDD MOS FET of FIG. 1, focussed on the drain diffusion region, while FIG. 3(b) is a diagram in which distances along the horizontal axis corresponds to those of FIG 3(a) and which shows the distribution of electric field in the structure of FIG. 3(a). When a high voltage is applied between the source and drain diffusion regions 3, then due to the fact that the gate electrode 5a is coupled through a very thin layer of the oxide film to the lightly doped drain diffusion region 4 as shown in FIG. 3(a), a high value of electric field is produced within that diffusion region 4 at a position immediately below the outer end of the gate electrode 5a, due to the vertical and horizontal components of the electric field at that position. That very high level of electric field causes hot-electron emission, resulting in various problems as described hereinabove. PA1 (2) Due to the position at which that very high value of electric field is produced, i.e. immediately adjacent to the outer end of the gate electrode 5a, the hot electrons will be readily trapped in the thick side wall formed of oxide film which covers that end portion of the gate electrode. This trapping of hot electrons results in a substantial increase in the rate of degradation of the transistor. PA1 (3) Since depletion will readily occur within the lightly doped diffusion region 4, this constitutes a source of parasitic resistance. PA1 (1) Due to the fact that the lightly doped drain diffusion region 4 is completely covered by the gate electrode 5a, while separated therefrom by a thin oxide film, the stray capacitance between drain and gate is high, which results in problems such as increased delay time and increased power consumption. PA1 (2) As shown in the electric field FIG. 4(b), the vertical component of electric field within the lightly doped drain diffusion region 4 is increased due to the action of the gate electrode 5a, and when a voltage is applied to the gate electrode 5a for setting the transistor in the OFF state, with a high voltage bring applied to the drain diffusion region, then inter-band tunnelling will occur, which results in a drain leakage current, i.e. resulting in gate diode leakage being produced. PA1 a semiconductor substrate of a first conduction type, having formed in a major surface thereof highly doped drain and source diffusion regions, and lightly doped drain and source diffusion regions disposed mutually opposing and respectively adjoining said highly doped drain and source diffusion regions, each of said diffusion regions being of a second conduction type; PA1 a gate insulating layer formed on said major face of said semiconductor substrate; and PA1 a gate electrode formed on said gate insulating layer, said gate electrode having an underside formed in a downwardly protruding convex shape, with first and second outer parts of said underside disposed immediately above said lightly doped drain and source diffusion regions respectively, separated therefrom by respective thick regions of said gate insulating layer. PA1 (a) sequentially forming upon a major face of a semiconductor substrate that is of a first conduction type a first insulating film, a conducting film for use in forming a gate electrode, formed over said first insulating film, and a second insulating film formed over said conducting film; PA1 (b) forming a mask by photolithography and executing anisotropic etching using the mask, to a depth sufficient to selectively expose said first insulating film, to form a a portion of said conducting film as a gate electrode, with a portion of said second insulating film covering only a top face of said gate electrode; PA1 (c) forming over said gate electrode, said second insulating film portion thereon, and adjoining regions of said first insulating film, a third insulating film consisting of a material which is not readily permeable to oxygen; PA1 (d) executing anisotropic etching to selectively remove said third insulating film, leaving said third insulating film only upon side faces of said gate electrode and of said second insulating film portion; PA1 (e) executing ion implantation to form first and second highly doped diffusion regions of a second conduction type within said major face of the semiconductor substrate; PA1 (f) executing oxidation processing to oxidize outer end portions of an underside of said gate electrode, while side faces of said gate electrode extending above said end portions are protected from oxidation by said third insulating film, to thereby form thick oxide insulating film regions between said outer end portions of the gate electrode underside and said major face of the semiconductor substrate; and PA1 (g) executing large tilt angle ion implantation to form, in said major face of the semiconductor substrate, first and second lightly doped diffusion regions of said second conduction type, respectively adjoining said first and second highly doped diffusion regions, with said said lightly doped diffusion regions extending below respective ones of .said thick oxide insulating film regions. PA1 (a) forming upon a major face of a semiconductor substrate that is of a first conduction type a first insulating film and forming upon said first insulating film a second insulating film; PA1 (b) forming a patterned mask by photolithography at predetermined positions on the second insulating film, and executing strongly anisotropic etching through the mask in the vertical direction to a sufficient depth to expose the first insulating film, for thereby forming an opening in the second insulating film; PA1 (c) forming over regions including said opening in the second insulating film an upper film having an etching ratio that is different from those of said first and second insulating films; PA1 (d) executing strongly anisotropic etching in the vertical direction to remove said upper film from positions other than side faces of said second insulating film; PA1 (e) executing strongly anisotropic etching in the vertical direction of the first insulating film using said second insulating film and said upper film as a mask, to thereby form an opening in said first insulating film which is concentric with and smaller than said opening in the second insulating film; PA1 (f) executing oxidation of a region including said opening in the second insulating film, to form a thin region of the first insulating film on said substrate main face within said opening in the first insulating film; PA1 (g) filling said apertures in the first and second insulating films with a conducting material to form a gate electrode; PA1 (h) executing etching to completely remove said second insulating film; PA1 (i) executing large slant angle ion implantation to form lightly doped first and second diffusion regions of a second conduction type, mutually opposing within said main face of the semiconductor substrate, said first and second lightly doped diffusion regions each extending to respective positions below said thin region of the first insulating film; PA1 (j) forming a third insulating film over a region including said gate electrode; PA1 (k) executing strongly anisotropic etching in the vertical direction of the third insulating film, leaving the third insulating film remaining only on side faces of said gate electrode; and PA1 (l) executing ion implantation into said main face of the semiconductor substrate, to form first and second highly doped diffusion regions of the second conduction type, respectively adjoining said first and second lightly doped diffusion regions. PA1 (a) forming upon a major face of a semiconductor substrate that is of a first conduction type a first insulating film, and successively forming upon said first insulating film as a multilayer set of films a first conducting film and a second conducting film, said second conducting film having an etching ratio that is different from said first conducting film; PA1 (b) etching said multilayer set of films at predetermined positions using a photolithography mask, to a depth sufficient to expose said first insulating film, by anisotropic etching, to form a gate electrode from said mutlilayer set of films; PA1 (c) etching mutually opposing end portions of said first conducting film of said gate electrode, while leaving said second conducting film of the gate electrode unchanged, to thereby form an underside of said gate electrode to a downwardly protruding convex shape, as seen in cross-sectional view; PA1 (d) executing large slant angle ion implantation to form first and second lightly doped diffusion regions of a second conduction type in said major face of the semiconductor substrate, such that said diffusion regions extend to respective positions below said first conducting film of the gate electrode; PA1 (e) executing fellow thermal processing to form a second insulating film of a material suitable for fellow processing, over a region including said gate electrode, with said second insulating film being formed to a greater thickness over said first insulating film than over a top face of said gate electrode; PA1 (f) forming a third insulating film over a region including said gate electrode; PA1 (g) executing etching to remove said third insulating film from all regions other than side portions of said second insulating film which cover side faces of said gate electrode, using strongly anisotropic etching in the vertical direction; PA1 (h) executing ion implantation to form first and second highly doped diffusion regions of the second conduction type, respectively adjoining said first and second lightly doped diffusion regions, in said major face of the semiconductor substrate. PA1 (a) forming upon a major face of a semiconductor substrate that is of a first conduction type a first insulating film, and successively forming upon said first insulating film as a multilayer set of films a first conducting film and a second conducting film, with said second conducting film being formed of a material that is not readily oxidized; PA1 (b) etching said multilayer set of films at predetermined positions using a photolithography mask and a strongly anisotropic etching method, to a depth sufficient to expose said first insulating film, to form a gate electrode from said mutlilayer get of films; PA1 (c) executing large slant angle ion implantation to form first and second lightly doped diffusion regions of a second conduction type in said major face of the semiconductor substrate, such that said diffusion regions extend to respective positions below said first conducting film of the gate electrode; PA1 (d) executing oxidation processing to oxidize opposing end portions of said first conducting film of the gate electrode while leaving said second conducting film unchange, to thereby form said gate electrode with an underside having a downwardly protruding convex shape; PA1 (e) forming a second insulating film over a region including said gate electrode; PA1 (f) executing strongly anisotropic etching in the vertical direction, to remove said second insulating film from all regions other than side faces of said gate electrode; PA1 (g) executing ion implantation to form first and second highly doped diffusion regions of the second conduction type, respectively adjoining said first and second lightly doped diffusion regions, in said major face of the semiconductor substrate. PA1 (1) Due to the fact that the underside of the gate electrode of the transistor is formed in a downwardly-protruding convex shape, a reduction can be achieved in the amount of stray capacitance between the drain and gate electrode which arises due to portions of the gate electrode being disposed closely adjacent to the lightly doped drain diffusion region, since the part of the gate electrode that is most closely adjacent to that lightly doped diffusion region is separated therefrom by a thick insulating film. Moreover, the presence of that think insulating film between the lightly doped drain diffusion region and the most closely adjacent part of the gate electrode serves to reduce the value of the vertical component of electric field which is produced within that lightly doped diffusion region, and to reduce energy band curvature, thereby reducing the concentration of electric field within the lightly doped drain diffusion region. PA1 (2) In the case of an embodiment of the present invention in which the upper side of the gate electrode is formed in an upwardly, protruding convex shape, a greater amount of separation is provided between the gate electrode and any connecting lines which are formed above the gate electrode, thereby serving to reduce the amount of stray lead capacitance. PA1 (3) In the case of an embodiment of the present invention in which the portions of the gate electrode that are disposed closely adjacent to the lightly doped source and drain diffusion regions are formed of a material having a higher value of work function than that of a downwardly protruding portion of the gate electrode, in the case of a p-type semiconductor substrate, or are formed of a material having a lower value of work function than that of the downwardly protruding portion of the gate electrode, in the case of an n-type semiconductor substrate being used, the effective level of voltage applied from the gate electrode to the lightly doped source and drain diffusion regions is effectively reduced, so that the concentration of electric field in the drain region can be reduced. PA1 (4) Currently used types of LSI manufacturing process can be easily adapted for manufacturing MOS FETs according to the present invention, for example by successively:
Referring to FIG. 4, FIG. 4(a) is a partial cross-sectional view of the prior art Inverse-TMOS FET Of FIG. 2, focussed on the drain diffusion region, while FIG. 4(b) is a diagram in which distances along the horizontal axis corresponds to those of FIG. 4(a) and which shows the distribution of electric field in the structure of FIG. 4(a). With such a structure, the following problems arise:
Thus, both of these prior art types of MOS FET which attempt to prevent deterioration of performance in spite of miniaturization of the MOS FET structure, by the addition of lightly doped n-type diffusion regions at the drain and source diffusion regions, have respective disadvantages.